1. Field of the Invention
The present invention relates to a method for forming a bit line for a semiconductor device and, in particular, to an improved method for forming a bit line for a semiconductor device that also improves the contact process for the semiconductor device.
2. Description of the Background Art
If the minimum line width of a conventional DRAM cell is xe2x80x98Fxe2x80x99, then the size of the unit cell will typically be approximately 10F2.
Recent work has led to suggestions for a method of reducing the cell size to 8F2. It appears that a cell size reduction from of 10F2 to a cell size of 8F2 may be achieved without fundamentally changing the conventional processes and concepts.
However, a new cell layout and process concept are required in order to reduce the cell size to 6F2. That is, using conventional methods, the cell size of 6F2 cannot be employed successfully for a highly integrated device.
Accordingly, it is an object of the present invention to provide a method for forming a bit line for a semiconductor device that can be used to fabricate a highly integrated semiconductor device having a cell size of 6F2, by forming I-type active regions and a ladder-type bit line contacting the active regions in order to simplify subsequent contact processing.
In order to achieve the above-described object of the present invention, there is provided a method for forming a bit line for a semiconductor device, including the steps of: forming I-type active regions having a minimum line width on a semiconductor substrate, each active region being separated from adjacent active regions by the minimum line width distance; forming word lines having a minimum line width that are generally perpendicular to the I-type active regions, a pair of word lines crossing each I-type active region that leave three portions of the I-type active region exposed; forming a plug poly (polysilicon) on the active region between the word lines; forming an interlayer insulation film over the resultant structure; forming a bit line contact plug that overlaps the plug poly by a predetermined width; and forming a bit line having a minimum line width that overlaps the bit line contact plug by a predetermined width, the bit lines being oriented generally perpendicular to the word lines and generally parallel to the I-type active regions.